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Client Setup

Where Some things go and how to name them

General Notes

• All assets in the vault must have a name and be placed in a folder that is not the default/root

• The more specific the folder/type the better

  • Don’t make new folders, but do make sure you aren’t picking a top level folder if there is a good match lower in the tree

• Names should be generic if possible

  • For example the TPS5V converter that comes in a few voltages could be named TPSXX so the symbol is sharable among all versions

  • A footprint for a MOSFET that is a three pin TO-220 should just be labeled “TO-220-3” so it can be reused for other FETs and diodes, rather than a specific MPN

Components

Follows the Digikey product to help you get started

Below is a download of our standard settings file. This automatically sets up your local client settings, such as default templates, color schemes, etc.

This file is also available directly in the vault at: X

XXXX

Directions for use are covered in https://nerdocs.atlassian.net/wiki/spaces/NER/pages/3932597/Altium+Designer#Install-%26-Setup.

The following expand details notes on what we configured in this download.

Vault Organization

Where things go and how to name them

General Notes

• All assets in the vault must have a name and be placed in a folder that is not the default/root

• The more specific the folder/type the better

  • Don’t make new folders, but do make sure you aren’t picking a top level folder if there is a good match lower in the tree

• Names should be generic if possible

  • For example the TPS5V converter that comes in a few voltages could be named TPSXX so the symbol is sharable among all versions

  • A footprint for a MOSFET that is a three pin TO-220 should just be labeled “TO-220-3” so it can be reused for other FETs and diodes, rather than a specific MPN

Components

Follows the Digikey product categories.

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Deprecated. We now embed 3D models directly into footprints.

Components

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Saving Items

Projects, components, symbols, and everything else in Altium are all managed in the version control system. Anytime you save to server you will be prompted to enter a commit comment.

You must add a note briefly detailing changes you made on all commits!

Components

Requirements for component files. See https://nerdocs.atlassian.net/wiki/spaces/NER/pages/118718470/Vault+Guidelines#Symbols.1 and https://nerdocs.atlassian.net/wiki/spaces/NER/pages/118718470/Vault+Guidelines#Footprints.1 for the symbols and footprints you embed!

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Symbol Layout

Symbols should use imperial spacing at 100 mils.

If a more detailed symbol isn’t available, footprints should be implemented using the Altium default yellow rectangle with “small” red outline.

Pins

Pins should be spaced by one 100 mil grid spacing.

Pin designators should be hidden and pin names should exactly match the datasheet (with the exception of characters that Altium doesn’t allow).

Pin arrangement can be either matching the physical layout or optimized for schematic routing (place pins as needed to avoid messy wires).

All pins must be passive type.

Designators

Utilize common designators for symbols. The hard-set definition we use is Appendix F of IEEE-315:

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The right side column is what we utilize, when applicable.

All designator letters should must be followed by “?”, as this is the wildcard for auto-generating designators. For example “D?” for diodes, “J?” for connectors, “R?” for resistors.

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Solder mask relief must be set to “Rule.” Exceptions should only be made if a component datasheet requests exact values.

Plated Through Holes

Annular ring (the difference in radius between pad radius and hole radius) should be 12 mils / 0.3 mm. Fabricators specify a smaller size which we can use, but we recommend this size for ease of hand solderability.

This means you should take hole size (diameter) and add 0.6mm. See https://www.worthingtonassembly.com/plated-thru-hole-size for more.

Given a pin diameter, the hole size should be determined by adding 0.2mm.

Mounting & GND Pads

If a component requires additional pads that are not regular electrical connections, they must be defined as “GND” or as “MNT” dependent on purpose of the pad. They may be MNT1, MNT2, etc to keep unique identifiers.

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Pin one ideally is also indicated via pads with a rectangular/square pad (with the other pads being ovular/circular). This is most typical in through-hole components.

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For hierarchical designs, we require the designators to be set to the format of [Type Letter][Instance Number][Sheet Letter]. This is done during the project level annotation process (https://nerdocs.atlassian.net/wiki/spaces/NER/pages/136314883/Schematic+Capture#Designating-Hierarchical-Documents) using the query $Component$Alpha.

Notes

We approve of two styles for notation. These can be used in conjunction, if the need arises.

Reference Based

Add a large Notes block to the schematic. Then add small numbers to locations in the schematic page you would like to refer to. The corresponding numbers can then be listed in order in the large notes block with commentary.

Reference numbers should be green and in parenthesis, placed with the normal text tool.

An example of these method can be seen in the above figure, “Example sheet with functional subsections”

Color Coded

Add smaller Notes blocks directly where the note is required. Add your commentary to these blocks and downsize them to match the quantity of text needed (make the text fill the block).

These notes should be color coded for visual clarity as follows:

If this method is used, a legend should be added to the top sheet using notes blocks.

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Layout

Design Rules

Design rules must start at fabrication limits. Typically we base off JLCPCB’s capabilities.

Depending on project requirements, rules should be made more conservative. For example, expanding minimum clearance if the board has space to enable more conservative clearances.

Never reduce clearances or any other rules beyond official manufacturer capability without significant consideration and discussion.

Rules violations should never be waived. It is best to discuss the design rule causing violations, and then create additional rules, with corresponding documentation in Altium or in Confluence, to negate the violations.

Preset Design Rule Files

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Layout

There is far too much to cover in good layout. Therefore these will just highlight some high level items:

• Electrical requirements, such as differential pairs, filtering, and avoidance of parasitic/coupling should take precedence in layout.

• However, designers must take care to preserve aesthetics in layout. Ultimately, a clean looking board is a big part of the first impression we make on design judges

• Alignment tools must be used to perfectly align and space components

• Design rules will default to the minimum of what is manufacturable. It is best practice to increase trace widths and clearances wherever possible. You can even increase design rules if board space allows.

Silkscreen

Designators

All designators should be shown.

Font style should be stroke, and font size may be adjusted according to density. Additionally, pointers can be used to place designators around dense regions. Never alter a layout to fit designators; they are nice to have, but always less important than board functionality.

Ensure you stay within fabrication limits when changing font size. If density is exceedingly prohibitive, designators can be omitted.

Logos and Attribution

All boards must include at least 1 NER logo.

All boards should include the names of board layout contributors. We require the format of first initial, followed by abbreviated class year. I.e. “M. McCauley '23” for Matt McCauley, class of 2023using the query $Component$Alpha.

Notes

We approve of two styles for notation. These can be used in conjunction, if the need arises.

Reference Based

Add a large Notes block to the schematic. Then add small numbers to locations in the schematic page you would like to refer to. The corresponding numbers can then be listed in order in the large notes block with commentary.

Reference numbers should be green and in parenthesis, placed with the normal text tool.

An example of these method can be seen in the above figure, “Example sheet with functional subsections”

Color Coded

Add smaller Notes blocks directly where the note is required. Add your commentary to these blocks and downsize them to match the quantity of text needed (make the text fill the block).

These notes should be color coded for visual clarity as follows:

If this method is used, a legend should be added to the top sheet using notes blocks.

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Layout

Design Rules

Design rules must start at fabrication limits. Typically we base off JLCPCB’s capabilities.

Depending on project requirements, rules should be made more conservative. For example, expanding minimum clearance if the board has space to enable more conservative clearances.

Never reduce clearances or any other rules beyond official manufacturer capability without significant consideration and discussion.

Rules violations should never be waived. It is best to discuss the design rule causing violations, and then create additional rules, with corresponding documentation in Altium or in Confluence, to negate the violations.

Preset Design Rule Files

Layout

There is far too much to cover in good layout. Therefore these will just highlight some high level items:

• Electrical requirements, such as differential pairs, filtering, and avoidance of parasitic/coupling should take precedence in layout.

• However, designers must take care to preserve aesthetics in layout. Ultimately, a clean looking board is a big part of the first impression we make on design judges

• Alignment tools must be used to perfectly align and space components

• Design rules will default to the minimum of what is manufacturable. It is best practice to increase trace widths and clearances wherever possible. You can even increase design rules if board space allows.

Silkscreen

Designators

All designators should be shown.

Font style should be stroke, and font size may be adjusted according to density. Additionally, pointers can be used to place designators around dense regions. Never alter a layout to fit designators; they are nice to have, but always less important than board functionality.

Ensure you stay within fabrication limits when changing font size. If density is exceedingly prohibitive, designators can be omitted.

Logos and Attribution

All boards must include at least 1 NER logo.

All boards should include the names of board layout contributors. We require the format of first initial, followed by abbreviated class year. I.e. “M. McCauley '23” for Matt McCauley, class of 2023.

Board Stackup

The board layer stack manager must be updated with realistic layer stackup. If impedance control is used, the dielectric constants must also be accurate.

The layer numbers of the PCB should also match those of our footprints (https://nerdocs.atlassian.net/wiki/spaces/NER/pages/118718470/Vault+Guidelines#Layer-Pair-Setup). If all footprints are compliant to these guidelines before importing to the PCB, this will happen automatically.

Board Outline

The board outline must be represented in a mechanical layer. For our boards this is typically M1. The board outline layer should include the outer boundary as well as any slots, cutouts, etc.

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