The Altium 365 Vault is where we store all component symbols and footprints used by the team. We have setup guidelines to ensure that all final PCBs have a unified and methodical layer system.

Currently our guidelines are still in Google Drive:

Additionally, the #Standards folder contains the custom NERvetica font and a pre-populated DRC file.

Welcome to the Official NER Vault Guidelines! This is the comprehensive guide on requirements for everything in Altium at NER.

The format of this guide will be very barebones as we want it to be a quick and absolute guide. Check out Altium Reference for friendlier refreshers on workflow, shortcuts, and more.

CONTENTS

Vault Organization

Where things go and how to name them

General Notes

• All assets in the vault must have a name and be placed in a folder that is not the default/root

• The more specific the folder/type the better

  • Don’t make new folders, but do make sure you aren’t picking a top level folder if there is a good match lower in the tree

• Names should be generic if possible

  • For example the TPS5V converter that comes in a few voltages could be named TPSXX so the symbol is sharable among all versions

  • A footprint for a MOSFET that is a three pin TO-220 should just be labeled “TO-220-3” so it can be reused for other FETs and diodes, rather than a specific MPN

Components

Follows the Digikey product categories.

Symbols

Organized by component category, with a few noteworthy omissions due to mergers. Passives for example contains the standard resistor and capacitor symbols and Mechanical contains heat sinks and mounting holes.

Footprints

Follows the Digikey product categories. Within categories, footprints are split by manufacturer for unique footprints. A large exception is made for semiconductors, as they all can share footprints. See the ICs, Semiconductors folder for these common footprints which are sorted by standards.

3D Models

Deprecated. We now embed 3D models directly into footprints.

Components

Requirements for component files. See https://nerdocs.atlassian.net/wiki/spaces/NER/pages/118718470/Vault+Guidelines#Symbols.1 and https://nerdocs.atlassian.net/wiki/spaces/NER/pages/118718470/Vault+Guidelines#Footprints.1 for the symbols and footprints you embed!

Types

A few notes on component types and templates

Always use the most specific “Type” that is applicable to your component. More specific types correspond to more specifically tailored templates that include more useful parameters.

In particular:

• DO NOT use the “Integrated Circuits” type, unless you truly cannot find a more specific category

• Note that within “PMIC” we have created “Voltage Regulators.” This includes LDOs and switching regulators (and any other topologies)

Selection

Manufacturability

Components should be selected with ease of manufacturing/in-house assembly in mind, namely:

• 0603 is the smallest chip size that is hand-solderable in bulk. 0402 and smaller is possible, but frustrating

• ICs should use legged versions when available

Environment

Components should be automotive rated (AEC-Q) when available

Recommended Series

Parameters

Shit Parameters

DO NOT ADD THESE. WE DON’T WANT THEM

• Datasheets (these often go out of date, so we require pulling from online)

• RoHS Compliant (not relevant)

• Reach SVHC Compliant (not relevant)

• Packaging (not relevant)

Symbols

Symbol Layout

Symbols should use imperial spacing at 100 mils.

If a more detailed symbol isn’t available, footprints should be implemented using the Altium default yellow rectangle with “small” red outline. Pins should be spaced by one 100 mil grid spacing.

Pin designators should be hidden and pin names should exactly match the datasheet (with the exception of characters that Altium doesn’t allow).

Pin arrangement can be either matching the physical layout or optimized for schematic routing (place pins as needed to avoid messy wires).

Designators

Utilize common designators for symbols. The hard-set definition we use is Appendix F of IEEE-315:

The right side column is what we utilize, when applicable.

All designator letters should be followed by “?”, as this is the wildcard for auto-generating designators. For example “D?” for diodes, “J?” for connectors, “R?” for resistors.

Footprints

All layers can adjust line width to be proportional to component size. Around 5 mils / 0.15mm is often a good starting point.

Layer Pair Setup

The following are the required layer pairs names and numbers as well as what to put in each.

Assembly

• Should be a 3D model downloaded from the manufacturer or other trusted site

• A 3D extrusion is allowable to approximate if no CAD can be found

• Additional physical assembly details can be included if required (designator indicators or other features)

Component Outline

Must match the physical outline of the component. This can be traced from 3D body, if the body is accurate. If legs are present, the legs should be disregarded (only trace the plastic/ceramic body)

Component Center

A crosshair must be added to all components. This consists of just two lines intersecting to create plus sign.

Courtyard

Collision box for placing components. This is a boundary that should define how much clearance is recommended between components.

Recommended: 10 mils / 0.25 mm

Pin 1 Designation

Pin one is usually indicated in the datasheet. If not, select the top left or top right corner from the footprint.
Pin one must be indicated in silkscreen. By default, this should be a circle next to pin one.

Pin one ideally is also indicated via pads with a rectangular/square pad (with the other pads being ovular/circular).

3D Model

All footprints must include a 3D model.

If manufacturer CAD is not available, add an extruded model and color it to a representative hue.

Schematics

All schematic sheets must use the NER template. Tabloid is the default, but Letter size is also available.

Multi-sheet/Hierarchy

Projects requiring multiple sheets should implement a hierarchical structure, utilizing a block-diagram style top sheet.

It is preferential to keep a design entirely on the top sheet, if it is small enough.

Functional sections on all pages should then be designated using medium red dashed lines to define boxes.

Style Guidelines

Schematics should default to a 100 mils grid system. The grid may be reduced for placing certain components, but components and wires must be aligned to a 100 mils grid.

Signal Routing

Within functional sections of the schematic, it is recommended to utilize wires to establish connections. For longer runs, or within densely connected regions, it is best to use Net Labels. Generally, wire routing just needs to be kept readable, however the designer thinks that is best achieved.

All connections of significance should be net labeled, even if connected via wire.

Wires must be stepped away from connections by at least 1 grid spacing (100 mils)

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Four way connections must be avoided.

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Net Labels

Net labels should be used anywhere they make sense, both for connections and for just labeling purposes.

Net labels should be in full caps with underscores to separate words and suffixes.

Acronyms may be used if full name would be excessively long. A note should be added to explain acronyms if they are not self explanatory.

Power & GND Ports

All power nets must be implemented using power ports.

The BAR power port must be used for all supply voltage nets. This includes positive and negative rails.

The GND port must be used for all GLV ground/chassis connections.

The SIGNAL ground port may be used in non-GLV ground systems. This primarily arises in isolated systems.

Communication Busses

Bussed signals, such as CAN, SPI, I2C, etc should utilize harnesses.

Addressed Devices (I2C)

Devices with addresses set in hardware must have their address stated above the component in blue text.

Component Placement

Components should be placed on a 100 mils grid.

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Annotations

All components must be assigned a unique designator. Use the integrated tools to complete this process automatically, as specified in https://nerdocs.atlassian.net/wiki/spaces/NER/pages/136314883/Schematic+Capture#Updating-Designators-(Annotation).

For hierarchical designs, we require the designators to be set to the format of [Type Letter][Instance Number][Sheet Letter]. This is done during the project level annotation process (https://nerdocs.atlassian.net/wiki/spaces/NER/pages/136314883/Schematic+Capture#Designating-Hierarchical-Documents) using the query $Component$Alpha.

Notes

We approve of two styles for notation. These can be used in conjunction, if the need arises.

Reference Based

Add a large Notes block to the schematic. Then add small numbers to locations in the schematic page you would like to refer to. The corresponding numbers can then be listed in order in the large notes block with commentary.

Reference numbers should be green and in parenthesis, placed with the normal text tool.

An example of these method can be seen in the above figure, “Example sheet with functional subsections”

Color Coded

Add smaller Notes blocks directly where the note is required. Add your commentary to these blocks and downsize them to match the quantity of text needed (make the text fill the block).

These notes should be color coded for visual clarity as follows:

If this method is used, a legend should be added to the top sheet using notes blocks.

Layout

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