Welcome to the Official NER Vault Guidelines! This is the comprehensive guide on requirements for everything in Altium at NER.

The format of this guide will be very barebones as we want it to be a quick and absolute guide. Check out Altium Reference for friendlier refreshers on workflow, shortcuts, and more.

CONTENTS

Client Setup

Some things to help you get started

Below is a download of our standard settings file. We highly recommend utilizing this to automatically setup your local client settings, such as default templates, color schemes, etc.

This file is also available directly in the vault at: X

XXXX

The following expand details notes on what we configured in this download.

Vault Organization

Where things go and how to name them

General Notes

• All assets in the vault must have a name and be placed in a folder that is not the default/root

• The more specific the folder/type the better

  • Don’t make new folders, but do make sure you aren’t picking a top level folder if there is a good match lower in the tree

• Names should be generic if possible

  • For example the TPS5V converter that comes in a few voltages could be named TPSXX so the symbol is sharable among all versions

  • A footprint for a MOSFET that is a three pin TO-220 should just be labeled “TO-220-3” so it can be reused for other FETs and diodes, rather than a specific MPN

Components

Follows the Digikey product categories.

Symbols

Organized by component category, with a few noteworthy omissions due to mergers. Passives for example contains the standard resistor and capacitor symbols and Mechanical contains heat sinks and mounting holes.

Footprints

Follows the Digikey product categories. Within categories, footprints are split by manufacturer for unique footprints. A large exception is made for semiconductors, as they all can share footprints. See the ICs, Semiconductors folder for these common footprints which are sorted by standards.

3D Models

Deprecated. We now embed 3D models directly into footprints.

Components

Requirements for component files. See https://nerdocs.atlassian.net/wiki/spaces/NER/pages/118718470/Vault+Guidelines#Symbols.1 and https://nerdocs.atlassian.net/wiki/spaces/NER/pages/118718470/Vault+Guidelines#Footprints.1 for the symbols and footprints you embed!

Types

A few notes on component types and templates

Always use the most specific “Type” that is applicable to your component. More specific types correspond to more specifically tailored templates that include more useful parameters.

In particular:

• DO NOT use the “Integrated Circuits” type, unless you truly cannot find a more specific category

• Note that within “PMIC” we have created “Voltage Regulators.” This includes LDOs and switching regulators (and any other topologies)

Selection

Manufacturability

Components should be selected with ease of manufacturing/in-house assembly in mind, namely:

• 0603 is the smallest chip size that is hand-solderable in bulk. 0402 and smaller is possible, but frustrating

• ICs should use legged versions when available

Environment

Components should be automotive rated (AEC-Q) when available

Recommended Series

Description

The description must contain useful information. Sometimes, the Altium database will have good data, but if not, default to copying the Digikey “Detailed Description” for the part.

Parameters

Shit Parameters

DO NOT ADD THESE. WE DON’T WANT THEM

• Datasheets (these often go out of date, so we require pulling from online)

• RoHS Compliant (not relevant)

• Reach SVHC Compliant (not relevant)

• Packaging (not relevant)

What Value to Use

Numerical Values

All parameters must be filled in using values from normal/recommended operation. This means the “Absolute Max” table or values should not be used.

If one parameter field is provided and the datasheet provides typical, min/max, and absolute min/max, think about what is most informative when searching for components for a new design. Typically, the minimum/maximum of normal range!

Case/Package Value

Digikey may provide multiple different values for this field. Our protocol is to first check if we have an existing footprint for the component. If so, enter the standard footprint name that was used. If not, use whichever name is most commonized (avoid manufacturer proprietary names).

Symbols

Symbol Layout

Symbols should use imperial spacing at 100 mils.

If a more detailed symbol isn’t available, footprints should be implemented using the Altium default yellow rectangle with “small” red outline.

Pins

Pins should be spaced by one 100 mil grid spacing.

Pin designators should be hidden and pin names should exactly match the datasheet (with the exception of characters that Altium doesn’t allow).

Pin arrangement can be either matching the physical layout or optimized for schematic routing (place pins as needed to avoid messy wires).

All pins must be passive type.

Designators

Utilize common designators for symbols. The hard-set definition we use is Appendix F of IEEE-315:

The right side column is what we utilize, when applicable.

All designator letters must be followed by “?”, as this is the wildcard for auto-generating designators. For example “D?” for diodes, “J?” for connectors, “R?” for resistors.

Properties

The component type must be set when applicable. This drop down allows you to define components as non-BOM items, such as mounting holes, test points, etc. We primarily use Standard, Net Tie (No BOM), and Standard (No BOM).

The Designator must be shown, however the Comment typically is hidden. The comment field determines if the component part number will be shown by default.

Footprints

All footprints must be modeled such that the component is installed on the top side of the board (footprints are a top view) and such that pin 1 is towards the top left.

All layers can adjust line width to be proportional to component size. 5 mils / 0.12mm is a good starting point.

Layer Pair Setup

The following are the required layer pairs names and numbers as well as what to put in each.

As mentioned above, we recommend a line width for all primitives of 5 mils / 0.12 mm. This can be adjusted proportionally to the overall component size if desired to avoid obscuring detail.

Assembly

Should be a 3D model downloaded from the manufacturer or other trusted site. A 3D extrusion is allowable to approximate if no CAD can be found.

Additional physical assembly details can be included if required (designator indicators or other assembly features). For context on what is acceptable, this is a layer that is purely used for reference by the company assembling the board. We typically only add a 3D model.

Component Outline

Must match the physical outline of the component. This can be traced from 3D body, if the body is accurate.

If this is a legged component, the legs should be disregarded (only trace the plastic/ceramic body)

Component Center

A crosshair must be added to all components. This consists of just two lines intersecting to create plus sign.

The component center should be placed at the center of all component pins.

The lines should default to 30 mils / 0.8 mm in length. This may be decreased or increased if the component is foolishly smaller or larger than these extents.

Courtyard

Collision box for placing components. This is a boundary that should define how much clearance is recommended between components.

Recommended spacing: 10 mils / 0.25 mm

Courtyards should be defined from the physical bounds of the component and pads. Silkscreen may be outside the courtyard if desired.

Pad Guidelines

Duplicate pads (pads representing the same net) should utilize unique identifiers, and be remapped at the component level. There can be an exception to this for mounting pads, however the trend for Altium seems to be to move fully to unique pad numbers.

Tolerance data is not necessary for any of our work. It should be left blank.

Solder mask relief must be set to “Rule.” Exceptions should only be made if a component datasheet requests exact values.

Through Holes

Annular ring (the difference in radius between pad radius and hole radius) should be 12 mils / 0.3 mm. Fabricators specify a smaller size which we can use, but we recommend this size for ease of hand solderability.

This means you should take hole size (diameter) and add 0.6mm. See https://www.worthingtonassembly.com/plated-thru-hole-size for more.

Mounting & GND Pads

If a component requires additional pads that are not regular electrical connections, they must be defined as “GND” or as “MNT” dependent on purpose of the pad. They may be MNT1, MNT2, etc to keep unique identifiers.

Pin 1 Designation

Pin one is usually indicated in the datasheet. If not, select the top left or top right corner from the footprint.

Pin one must be indicated in silkscreen. By default, this should be a circle next to pin one. The circle should be 20 mils / 0.5 mm in diameter.

Pin one ideally is also indicated via pads with a rectangular/square pad (with the other pads being ovular/circular). This is most typical in through-hole components.

3D Model

All footprints must include a 3D model. If manufacturer CAD is not available, add an extruded model and color it to a representative hue.

Origin

All layouts and footprints have an origin. This is where the coordinate system is zeroed from.

The origin may be moved throughout the layout process but when complete must be set to either the origin of the datasheet dimensions or the center of the component.

Schematics

All schematic sheets must use the NER template. Tabloid is the default, but Letter size is also available.

Organization & Hierarchy

Projects requiring multiple sheets should implement a hierarchical structure, utilizing a block-diagram style top sheet.

It is preferential to keep a design entirely on the top sheet, if it is small enough.

Functional sections on all pages should then be designated using medium red dashed lines to define boxes.

All schematics must be organized logically. This is typically either by placing in order of power and signal flow (inputs/supplies to the left, to outputs/loads on the right) or, for TS-GLV projects, by organizing according to isolation, placing all isolation barriers along a single line.

Style Guidelines

Schematics should default to a 100 mils grid system. The grid may be reduced for placing certain components, but components and wires must be aligned to a 100 mils grid.

Signal Routing

Within functional sections of the schematic, it is recommended to utilize wires to establish connections. For longer runs, or within densely connected regions, it is best to use Net Labels. Generally, wire routing just needs to be kept readable, however the designer thinks that is best achieved.

All connections of significance should be net labeled, even if connected via wire.

Wires must be stepped away from connections by at least 1 grid spacing (100 mils)

Four way connections must be avoided.

Net Labels

Net labels should be used anywhere they make sense, both for connections and for just labeling purposes.

Net labels should be in full caps with underscores to separate words and suffixes.

Acronyms may be used if full name would be excessively long. A note should be added to explain acronyms if they are not self explanatory.

All voltage rails should follow the below guidelines.

Power & GND Ports

All power nets must be implemented using power ports.

All power nets should be labeled using decimal-less notation. Examples are:

• +3V3 = Positive 3.3V

• +1V8 = Positive 1.8V

• +48V = Positive 48V

• -5V = Negative 5V

The BAR power port must be used for all supply voltage nets. This includes positive and negative rails.

The GND port must be used for all GLV ground/chassis connections.

The SIGNAL ground port may be used in non-GLV ground systems. This primarily arises in isolated systems.

Communication Busses

Bussed signals, such as CAN, SPI, I2C, etc should utilize harnesses.

Addressed Devices (I2C)

Devices with addresses set in hardware must have their address stated above the component in blue text.

Component Placement

Components should be placed on a 100 mils grid.

Certain parameters should be displayed for every type of component. These may be modified in certain contexts if shown data is completely irrelevant. I.e. resistors used for logic may not need to show power rating.

If no parameters are shown, the MPN should be shown instead.

All components must be annotated, as described below.

Annotations

All components must be assigned a unique designator. Use the integrated tools to complete this process automatically, as specified in https://nerdocs.atlassian.net/wiki/spaces/NER/pages/136314883/Schematic+Capture#Updating-Designators-(Annotation).

For hierarchical designs, we require the designators to be set to the format of [Type Letter][Instance Number][Sheet Letter]. This is done during the project level annotation process (https://nerdocs.atlassian.net/wiki/spaces/NER/pages/136314883/Schematic+Capture#Designating-Hierarchical-Documents) using the query $Component$Alpha.

Notes

We approve of two styles for notation. These can be used in conjunction, if the need arises.

Reference Based

Add a large Notes block to the schematic. Then add small numbers to locations in the schematic page you would like to refer to. The corresponding numbers can then be listed in order in the large notes block with commentary.

Reference numbers should be green and in parenthesis, placed with the normal text tool.

An example of these method can be seen in the above figure, “Example sheet with functional subsections”

Color Coded

Add smaller Notes blocks directly where the note is required. Add your commentary to these blocks and downsize them to match the quantity of text needed (make the text fill the block).

These notes should be color coded for visual clarity as follows:

If this method is used, a legend should be added to the top sheet using notes blocks.

Layout

Design Rules

Design rules must start at fabrication limits. Typically we base off JLCPCB’s capabilities.

Depending on project requirements, rules should be made more conservative. For example, expanding minimum clearance if the board has space to enable more conservative clearances.

Never reduce clearances or any other rules beyond official manufacturer capability without significant consideration and discussion.

Rules violations should never be waived. It is best to discuss the design rule causing violations, and then create additional rules, with corresponding documentation in Altium or in Confluence, to negate the violations.

Preset Design Rule Files

Layout

There is far too much to cover in good layout. Therefore these will just highlight some high level items:

• Electrical requirements, such as differential pairs, filtering, and avoidance of parasitic/coupling should take precedence in layout.

• However, designers must take care to preserve aesthetics in layout. Ultimately, a clean looking board is a big part of the first impression we make on design judges

• Alignment tools must be used to perfectly align and space components

• Design rules will default to the minimum of what is manufacturable. It is best practice to increase trace widths and clearances wherever possible. You can even increase design rules if board space allows.

Silkscreen

Designators

All designators should be shown.

Font style should be stroke, and font size may be adjusted according to density. Additionally, pointers can be used to place designators around dense regions. Never alter a layout to fit designators; they are nice to have, but always less important than board functionality.

Ensure you stay within fabrication limits when changing font size. If density is exceedingly prohibitive, designators can be omitted.

Logos and Attribution

All boards must include at least 1 NER logo.

All boards should include the names of board layout contributors. We require the format of first initial, followed by abbreviated class year. I.e. “M. McCauley '23” for Matt McCauley, class of 2023.

Board Stackup

The board layer stack manager must be updated with realistic layer stackup. If impedance control is used, the dielectric constants must also be accurate.

The layer numbers of the PCB should also match those of our footprints (https://nerdocs.atlassian.net/wiki/spaces/NER/pages/118718470/Vault+Guidelines#Layer-Pair-Setup). If all footprints are compliant to these guidelines before importing to the PCB, this will happen automatically.

Board Outline

The board outline must be represented in a mechanical layer. For our boards this is typically M1. The board outline layer should include the outer boundary as well as any slots, cutouts, etc.

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